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[Other resource] sobel

Description: 这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。-this is my own preparation for the 256 * 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.
Platform: | Size: 3135 | Author: 刘洋 | Hits:

[Communication] 曼彻斯特码

Description: 今天看了一下从fpga上下的曼彻斯特编解码的程序，感觉不是很清楚，仿真了一下，更迷茫了，大家看看为啥这程序要这么编呢？ 程序比较长，不过写的应该还是不错的，看了后应该有收获。 总的思路是这样： 1 通过一个高频的时钟检测wrn信号，如果检测到上升沿，则表明开始编码，将输入的8位数据转为串行，并编码，然后输出。 2 定时信号是从高频时钟16分频后得到的，在wrn上升沿后16分频使能，在编码结束后禁止分频输出。 3 no_bits_sent记录串行输出的位数，应该是从0010到1001输出串行信号，到1010时编码结束，输出tbre表明编码完成。 问题是no_bits_sent在到了1010后还是会继续增加，直到1111，然后clk1x_enable 就为0，无法分频，clk1x就为一直流信号。这样当clk1x_enable再次为1的时候，no_bits_sent也不会增加，在1111上不变，clk1x_enable又会回到0了。 -today they simply watched from across the Manchester encoding and decoding process, not feeling very well, simulation a bit more confused, we look at procedures to be ready this series so? Procedures longer, but should still write good, it should have read harvest. The thinking is this : one by a high-frequency clock signal detection international, if detected rising edge, it indicates the beginning of coding will be entered into the eight to serial data and coding, and then output. Two timing signals from the high-frequency clock frequency 16 hours after the the international rising edge after 16 minutes frequency to enable the coding after the end of Prohibition-frequency output. 3 no_bits_sent record median serial output, it should be from 0010 to 1001 serial output signal to the end of
Platform: | Size: 5120 | Author: 游畅 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。-this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.
Platform: | Size: 3072 | Author: 刘洋 | Hits:

[Graph Recognize] paper

Description: 火灾图像边缘检测和轮廓提取算法研究.pdf 基于火焰图像动态特征的火灾识别算法.pdf-Fire image edge detection and contour extraction algorithm. Pdf flame image based on the dynamic characteristics of the fire recognition algorithms. Pdf
Platform: | Size: 789504 | Author: 明明 | Hits:

[Software Engineering] Digital_Filter_implementation_by_FPGA

Description: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on fpgas 5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages 6. implementing 2D median filter in fpgas 7.视频图像处理与分析的网络资源
Platform: | Size: 1969152 | Author: carol | Hits:

[VHDL-FPGA-Verilog] TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA

Description: Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.-Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.
Platform: | Size: 28409856 | Author: ramanaidu | Hits:

[VHDL-FPGA-Verilog] sobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:

[VHDL-FPGA-Verilog] Code_for_MedianFilter33

Description: 包含边缘探测的中值滤波FPGA工程，分辨率1024x16-Contains the edge detection filter in the value of the FPGA project
Platform: | Size: 54272 | Author: | Hits:

[VHDL-FPGA-Verilog] orcad_tutor

Description: A CODE FOR EDGE DETECTION IN FPGA
Platform: | Size: 1499136 | Author: seher | Hits:

[VHDL-FPGA-Verilog] edge_tech_design

Description: verilog的边沿检测技术，在fpga信号处理中应用相当的大,这也是一门艺术-the the verilog edge detection technology, in fpga signal processing is quite large, and this is an art
Platform: | Size: 37888 | Author: 磨国钰 | Hits:

[VHDL-FPGA-Verilog] key_scan

Description: 这个是学习FPGA时候自己写的键盘扫描的代码。采用的是边沿检测的方法,并且进行了滤波处理，本人测试仿真成功！-This is when the FPGA write their own learning keyboard scan code. Use is edge detection method, and its filtering processing, I test simulation success!
Platform: | Size: 367616 | Author: xie hao | Hits:

[VHDL-FPGA-Verilog] Grayscale-Conversion-IP

Description: Sobel Edge Detection IP for FPGA using LABVIEW
Platform: | Size: 26624 | Author: refaat | Hits:

[Windows Develop] tsobbellh

Description: 这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合与与仿真，并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测，同时还能实现其它的图像模块化处理算法，例如高斯滤波，平滑等。 -This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.
Platform: | Size: 3072 | Author: 兴奋 | Hits:

[VHDL-FPGA-Verilog] edge-detection1

Description: 基于FPGA开发环境，根据Sobel model算法，关于边缘检测的verilog代码。-the code of edge detection based on verilog.
Platform: | Size: 1024 | Author: Oscar | Hits:

[VHDL-FPGA-Verilog] Extras_Edge_Detection

Description: Altera Edge Detection for FPGA
Platform: | Size: 1120256 | Author: frozeus | Hits:

[VHDL-FPGA-Verilog] Edge_Detection

Description: FPGA code for Image Edge Detection
Platform: | Size: 181248 | Author: huythuong | Hits:

[VHDL-FPGA-Verilog] soble

Description: 基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)
Platform: | Size: 5868544 | Author: 我是陌陌同学 | Hits:

[VHDL-FPGA-Verilog] ece5760-final-cwf38-mao65-as889

Description: BALL GAME + EDGE DETECTION FOR FPGA
Platform: | Size: 14389248 | Author: chun354 | Hits:

[Other] edge

Description: FPGA实现下降沿边沿检测源代码，包含工程(FPGA implements edge detection source code, including engineering)
Platform: | Size: 289792 | Author: 任小刀 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:
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